1. Field
One or more embodiments of the present invention relate to the field of memory devices and more particularly to a system and method for controlling a delay locked loop (DLL) in a dynamic random access memory (DRAM) device.
2. Discussion of Related Art
In high performance digital systems, the timing synchronization between various electronic devices is an important design criteria for maintaining system performance. For example, the output of a memory device has to be synchronized to the system clock in order to prevent operation errors and delays that affect the overall system performance.
The memory device, in particularly a dynamic random access memory (DRAM) device, implements a delay locked loop (DLL) that synchronizes the DRAM output to the system clock. The DLL monitors the system clock signal received by the DRAM device and synchronizes its output clock signal to the system clock signal so as to ensure that the data output from the DRAM device is synchronized to the system clock. Typically, the DLL comprises a feedback loop that monitors an input clock signal, which is usually the system clock, and adjusts its output clock signal to be in phase to the input clock signal.
For the DRAM, the DLL helps to control the read return timing and on-die termination (ODT) operations. Hence, the DLL improves the bus turnaround time and the overall system performance. However, during the operation of the DRAM, the DLL constantly receives power in order to maintain synchronization between DRAM output and the system clock. Thus, the DLL contributes to the extensive power consumption by the DRAM that also requires constant power to maintain data content. A memory developer could implement a DLL-off mode to bypass the whole DLL in order to save power but this would result in asynchronous timing between the read return timing and ODT.